Design of a Low Power Adiabatic Logic Circuit Based on FinFET

The rapid development of transistor technology has resulted in higher performance and integration density. Simultaneously, the continuous increasing power has become the primary barrier against further development of VLSI (Very large scale integration) circu it design. Over the past decade, research work concerning energy efficiency of computing systems has increased. From big data centers with many servers to small battery operated mobile devices power dissipation is becoming a major concern. For dig ital IC’s design many low power design techniques have been proposed from t ime to time one of them which is suitable for u ltralow power applicat ions and is thus gaining attention is adiabatic logic. A number of different adiabatic logic styles have been proposed.Adiabatic logic style is an attractive solution for low power digital design. A novel low-power ad iabatic logic based on FinFETs (Fin-type Field-Effect Transistors) devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, The proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS (Complementary metal oxide semiconductor) adiabatic logic. In th is proposed work, we use 32nm pred ictive Technology model. And also analyzing the power dissipation of different adiabatic logic based on CMOS and FinFETs